1. Field of the Invention
The present invention relates to a method of manufacturing an electrically erasable programmable read only memory (EEPROM) cell, and more particularly, to a method of manufacturing an EEPROM cell, which forms a tunneling oxide layer using an improved process so as to enhance the write/erase efficiency of the EEPROM cell.
2. Description of the Related Art
A typical EEPROM cell includes a floating gate, a select gate, a tunneling oxide layer, a coupling oxide layer, a control gate, and a bit line. The floating gate stores charge in the form of electrons, and the select gate is formed on the floating gate to control the floating gate. The tunneling oxide layer functions as a path through which electrons are moved based on the Fowler-Nordheim tunneling (F-N tunneling) mechanism during a write or erase operation. The coupling oxide layer transmits a voltage applied to the select gate to the floating gate. The control gate transmits a bit line voltage during the write or erase operation. The bit line transmits data.
During a read or write operation, the control gate transmits data from the bit line to a cell or transmits data from the cell to the bit line. Since this control gate is connected to several cells orthogonal to the bit line and includes one or more words, it is referred to as a word line. The coupling oxide layer, which is formed on the floating gate, couples the voltage applied to the select gate during an erase operation to elevate the electric potential of the floating gate. In a typical EEPROM cell, an oxide-nitride-oxide (ONO) layer is used as a coupling oxide layer. Under the floating gate, a thick oxide region and a thin oxide region (i.e., a tunneling oxide region) are disposed. The thick oxide region reduces the coupling ratio between the voltage applied from the bit line and the voltage of the floating gate to maintain a large electric potential therebetween. Also, the thin oxide region functions as a path through which electrons move based on the F-N tunneling mechanism during a write or erase operation.
Hereinafter, a method of manufacturing a conventional EEPROM cell will be described with reference to FIGS. 1 through 5.
Referring to FIG. 1, a thick oxide layer 11 is grown on a silicon substrate 10 to a thickness of about 250 Å.
Referring to FIG. 2, a first photoresist mask 12 is formed such that the substrate 10 and the thick oxide layer 11 are exposed in a predetermined region. Impurity ions 13 are implanted into the exposed portion, thereby forming a floating junction 14 in the substrate 10. Then, the first photoresist mask 12 is removed.
Referring to FIG. 3, a second photoresist mask 16 is formed on the thick oxide layer 11 to define a tunneling oxide layer forming region 15. The thick oxide layer 11 in the tunneling oxide layer forming region 15 is wet etched using the second photoresist mask 16 as an etch mask so as to expose the floating junction 14. Then, the second photoresist mask 16 is removed.
Thereafter, a thin oxide layer is grown in the tunneling oxide layer forming region 15, thereby forming a tunneling oxide layer 17 as shown in FIG. 4. Over the substrate 10 on which the tunneling oxide layer 17 is formed, a first polysilicon layer 18 for a floating gate is formed. A coupling oxide layer 19, for example, an ONO layer, is formed thereon, and a second polysilicon layer 20 is formed to an appropriate thickness.
The second polysilicon layer 20, the ONO layer 19, and the first polysilicon layer 18 are patterned using a photolithography process. As a result, referring to FIG. 5, a select transistor S and a control transistor C are formed. The select transistor has a gate stack, which includes a select gate 20a, an ONO pattern 19a, and a floating gate 18a, and the control transistor C has a gate stack, which includes a control gate 20b, an ONO pattern 19b, and a floating gate 18b. Thereafter, an appropriate ion implantation process is performed to form a cell source junction 21 and a bit line junction 22. Consequently, an EEPROM cell is completed.
However, in the conventional EEPROM cell, the tunneling oxide layer 17 is formed on a portion of the substrate 10 from which a portion of the thick oxide layer 11 is removed using wet etching. Accordingly, the tunneling oxide layer 17 is not actually formed to the same size as that of the tunneling oxide layer forming region 15 defined by the second photoresist mask 16 and at a predetermined thickness. This is because after the thick oxide layer 11 is wet etched, not only the exposed portion in the tunneling oxide layer forming region 15 is etched, but also an adjacent region can be over-etched or an undercut can be formed. As shown in FIG. 6, which is an exploded view of the select transistor S shown in FIG. 5, the resultant tunneling oxide layer 17 has a greater size B than a size A of the tunneling oxide layer forming region 15 defined in FIG. 5. Also, an etching profile obtained by wet etching the thick oxide layer 11 is inclined so that the thickness of the tunneling oxide layer 17 is greater near the edge portions than in the center portion. Thus, the coupling ratio is reduced, which can deteriorate the write/erase efficiency of the EEPROM cell.
In general, the coupling ratio is a factor that determines the voltage that is to be applied to the tunneling oxide layer 17 during a write or erase operation. The voltage applied to the tunneling oxide layer 17 during a write operation (i.e., Vtun(write)) and the voltage applied to the tunneling oxide layer 17 during an erase operation (i.e., Vtun(erase)) are expressed as shown in Equations 1 and 2.Vtun(write)=Vfg+Kw×Vbl  (1)Vtun(erase)=Vfg+Ke×Vsl  (2)
Herein, Vfg refers to a voltage applied to the floating gate 18a, Kw refers to a coupling ratio during a write operation, Vbl refers to a bit line voltage, Ke refers to a coupling ratio during an erase operation, and Vsl is a voltage applied to the select gate 20a. Kw and Ke are expressed as shown in Equation 3.Kw=1−Ctun/(Cono+Cgox+Ctun)Ke=Cono/(Cono+Cgox+Ctun)  (3)
Herein, Cono refers to the capacitance of the ONO pattern 19a, Cgox refers to the capacitance of the thick oxide layer 11, and Ctun refers to the capacitance of the tunneling oxide layer 17.
As can be seen from Equations 1, 2, and 3, the coupling ratio depends on the capacitance of a capacitor constituting the select transistor S. As a capacitance Ctun increases, both Kw and Ke decrease to lower write/erase efficiency. To prevent this problem, it is required to form the tunneling oxide layer 17 to a small size and thickness. However, in the conventional method using wet etching, the tunneling oxide layer 17 is formed to a relatively large size and thickness to reduce the coupling ratio. As a result, write/erase efficiency is deteriorated.
Also, when the tunneling oxide layer 17 is formed to a large size, the overlap margin between the tunneling oxide layer 17 and the floating junction 14 decreases so that the resulting cell size cannot be sufficiently reduced. Further, if a boundary of the floating junction 14 is positioned under the tunneling oxide layer 17 due to the small overlap margin, the EEPROM cell becomes unreliable due to band-to-band tunneling (BTBT).